Low temperature Si device fabrication
EMSL Project ID
16094
Abstract
There is a demand for high performance semiconductor devices which are thin and flexible, for applications where high frequency operation, light weight, and conforming to a curved surface is required. (e.g., phase array radar, sensor networks.) It would be very beneficial, in terms of cost and performance, if it were possible to simultaneously fabricate arrays of such devices on large substrates. Polycrystalline silicon (poly-Si) thin-film-transistors (TFT) are attracting considerable attention for applications such as liquid crystal displays. The technology inherits the potential advantage of silicon-on-insulator (SOI) technology such as high density, easy isolation, simple process and the potential use of vertical integration. For cost effectiveness, low temperature production of TFTs is critical. It is believed that the electrical properties of poly-Si can be improved if the average grain size can be enhanced. (i.e., the number of grain boundaries can be minimized.) To achieve the above goals, a high temperature and long anneal process of poly-Si could be adopted metallurgically. But it is not economic in terms of the fabrication cost as well as a non-ideal method for the scaling devices due to the high diffusion length. Fortunately, intensive studies have been made to lower the crystallization temperature of amorphous silicon (a-Si) films. Metal induced- crystallization (MIC) is one technique that has been found successful. Recent development of MIC techniques represented an important breakthrough in Si technology because of it's ability of forming poly-Si at lower temperature. Liu et al. [1] first discovered the reduction of crystallization temperature of Si film from 700
Project Details
Project type
Exploratory Research
Start Date
2005-07-20
End Date
2006-07-24
Status
Closed
Released Data Link
Team
Principal Investigator
Team Members